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| LPR520 DEVICES INCORPORATED 4 x 16-bit Multilevel Pipeline Register LPR520 DEVICES INCORPORATED 4 x 16-bit Multilevel Pipeline Register DESCRIPTION The LPR520 is functionally compatible with the L29C520 but have 16-bit inputs and outputs. The LPR520 is implemented in low power CMOS. The LPR520 contains four registers which can be configured as two independent, 2-level pipelines or as one 4-level pipeline. The Instruction pins, I1-0, control the loading of the registers. The registers may be configured as a four-stage delay line, with data loaded into R1 and shifted sequentially through R2, R3, and R4. Also, data may be loaded from the inputs into either R1 or R3 with only R2 or R4 shifting. Finally, I1-0 may be set to prevent any register from changing. The S1-0 select lines control a 4-to-1 multiplexer which routes the contents of any of the registers to the Y output pins. The independence of the I and S controls allows simultaneous write and read operations on different registers. FEATURES u Four 16-bit Registers u Implements Double 2-Stage Pipeline or Single 4-Stage Pipeline Register u Hold, Shift, and Load Instructions u Separate Data In and Data Out Pins u High-Speed, Low Power CMOS Technology u Three-State Outputs u 44-pin PLCC, J-Lead LPR520 BLOCK DIAGRAM REGISTER 1 REGISTER 2 TABLE 1. LPR520 INSTRUCTION TABLE I1 MUX I0 L H L H Description D(c)R1 HOLD D(c)R1 R1(c)R2 HOLD R1(c)R2 R2(c)R3 D(c)R3 HOLD R3(c)R4 R3(c)R4 HOLD 16 D15-0 L L REG 1 REG 2 REG 3 REG 4 H MUX 16 Y15-0 OE 2 H ALL REGISTERS ON HOLD REGISTER 3 REGISTER 4 S1-0 TABLE 2. S1 S0 L L H H L H L H OUTPUT SELECT Register Selected Register 4 Register 3 Register 2 Register 1 2 I1-0 CLK Pipeline Registers 1 08/02/2000-LDS.P520-C LPR520 DEVICES INCORPORATED 4 x 16-bit Multilevel Pipeline Register MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... -65C to +150C Operating ambient temperature ........................................................................................... -55C to +125C VCC supply voltage with respect to ground ............................................................................ -0.5 V to +7.0 V Input signal with respect to ground ........................................................................................ -3.0 V to +7.0 V Signal applied to high impedance output ............................................................................... -3.0 V to +7.0 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0C to +70C -55C to +125C Supply Voltage 4.75 V VCC 5.25 V 4.50 V VCC 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol VOH VOL VIH VIL IIX IOZ ICC1 ICC2 Parameter Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Current Output Leakage Current VCC Current, Dynamic VCC Current, Quiescent (Note 3) Test Condition VCC = Min., IOH = -2.0 mA VCC = Min., IOL = 8.0 mA Min 2.4 Typ Max Unit V 0.5 2.0 0.0 VCC 0.8 20 20 10 40 1.0 V V V A A mA mA Ground VIN VCC (Note 12) Ground VOUT VCC (Note 12) (Notes 5, 6) (Note 7) Pipeline Registers 2 08/02/2000-LDS.P520-C 432109876543210987654321 432109876543210987654321 432109876543210987654321 *DISCONTINUED SPEED GRADE Symbol Symbol Y15-0 tDIS 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 4321098765432121098765432109876543210987654321 Min DEVICES INCORPORATED COMMERCIAL OPERATING RANGE (0C to +70C) Notes 9, 10 (ns) SWITCHING CHARACTERISTICS 4 x 16-bit Multilevel Pipeline Register LPR520- 22 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 543210987654321 6543210987654321 6543210987654321 6 Min 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 6543210987654321 543210987654321 6543210987654321 6543210987654321 6 Min SWITCHING WAVEFORMS MILITARY OPERATING RANGE (-55C to +125C) Notes 9, 10 (ns) tDIS tENA tHD tSD tHI tSI tPW tSEL tPD tDIS tENA tHD tSD tHI tSI tPW tSEL tPD Parameter Parameter Three-State Output Disable Delay (Note 11) Three-State Output Enable Delay (Note 11) Data Hold Time Data Setup Time Instruction Hold Time Instruction Setup Time Clock Pulse Width Select to Output Delay Clock to Output Delay Three-State Output Disable Delay (Note 11) Three-State Output Enable Delay (Note 11) Data Hold Time Data Setup Time Instruction Hold Time Instruction Setup Time Clock Pulse Width Select to Output Delay Clock to Output Delay D15-0 CLK S1-0 OE I1-0 tSD tSI tSEL tPD 3 tHI tHD tPW 15 13 15 13 15 10 5 3 5 3 30* 25* Max Max 20 25 25 25 30 25 30 25 tPW HIGH IMPEDANCE Min Min 10 10 10 10 10 10 LPR520- 24* 3 3 3 3 Pipeline Registers tENA Max Max 16 22 15 21 22 20 24 22 08/02/2000-LDS.P520-C Min 8 6 8 6 2 1 2 9 1 8 LPR520 18* 15* Max Max 13 16 18 15 12 15 18 15 LPR520 DEVICES INCORPORATED 4 x 16-bit Multilevel Pipeline Register NOTES 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of IOH and IOL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at -0.6 V and a. A 0.1 F ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of -0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a minN = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency 6. Tested with all outputs changing every cycle and no load, at a 5 MHz clock rate. 7. Tested with all inputs within 0.1 V of VCC or Ground, no load. 8. These parameters are guaranteed but not 100% tested. imum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. Responses from the internal circuitry are specified from the point of view of the device. Output delay, for example, is specified as a maximum since worst-case operation of any device always provides data within that time. 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the 200mV level from the measured steady-state output voltage with 10mA loads. The balancing voltage, VTH, is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT DUT S1 IOL CL IOH VTH FIGURE B. THRESHOLD LEVELS tENA OE Z 0 1.5 V 1.5 V 1.5 V tDIS 3.5V Vth VOL* 0.2 V 0 1 Z Z 1.5 V VOH* 0.2 V Z 1 0V Vth VOL* Measured VOL with IOH = -10mA and IOL = 10mA VOH* Measured VOH with IOH = -10mA and IOL = 10mA Pipeline Registers 4 08/02/2000-LDS.P520-C 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 654321098765432121098765432109876543210987654321 DEVICES INCORPORATED Speed 22 ns -55C to +125C -- MIL-STD-883 COMPLIANT -55C to +125C -- COMMERCIAL SCREENING 0C to +70C -- COMMERCIAL SCREENING LPR520 -- ORDERING INFORMATION 40-pin -- 0.6" wide Plastic DIP (P3) I0 I1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 CLK GND Discontinued Package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC S0 S1 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 OE Ceramic DIP (C11) 5 4 x 16-bit Multilevel Pipeline Register Plastic J-Lead Chip Carrier (J1) 44-pin LPR520JC22 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 NC 17 16 15 14 13 12 11 10 9 8 7 29 18 19 20 21 22 23 24 25 26 27 28 6 5 4 3 2 Top View 1 44 43 42 41 40 39 Pipeline Registers D13 D14 D15 CLK GND OE Y15 Y14 Y13 Y12 NC 30 31 32 33 34 35 36 37 38 08/02/2000-LDS.P520-C NC Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 NC D2 D1 D0 I1 I0 VCC S0 S1 Y0 Y1 LPR520 |
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